1. Field of the Invention
The present invention relates to the measurement of DRAM delay, more particular, to a method and a DRAM circuit for measuring the read operation delay on DRAM bit lines.
2. Description of Related Art
As the semiconductor technology migrates to deep-submicron and nanometer dimensions, as well as sub-nano second switching, VLSI (Very Large Scale Integrated circuits) interconnects have become one of the important limiting factors of modern high-speed and high-density circuit performance. Since the polysilicon/metal wires of integrated circuit are getting narrower, and the number of cells on the bit line of the integrated circuit are increasing, the interconnect RC delay may play a very significant role in circuit performance.
FIG. 6 shows a DRAM (Dynamic Random Access Memory) cell with a long polysilicon bit line (64). A bit is stored in a data capacitor (61). A word line (63) is provided to control the switching of the N-MOSFET (62). When the data bit is read out, the signal of the data bit needs to go through the polysilicon bit line (64) and reaches a sense amplifier. Since the inputs of a sense amplifier are the gates of MOSFETs, the equivalent circuit of the sense amplifier is a load capacitor (66). Consequently, the polysilicon bit line (64) consists of distributed RC and many junction capacitors from the sources of the MOSFETs, which are connected on the polysilicon bit line (64).
Currently, most of the analyses or measurement techniques are concentrated on either gates or RC distributed transmission lines. Recently, the measurement technique for CMOS SRAM (Static Random Access Memory) with interconnect propagation delay has been proposed, in which the delay is more than 10 nano-seconds, so it can be measured directly. Since the delay to be measured will be less than 1 nano-second, direct measurement is getting more difficult. Furthermore, the charging mechanisms are different for SRAMs and DRAMs. For read operations, the former uses inverters as drivers, and the later employs a data capacitor through an N-MOSFET to charge the bit line. The voltage variation for DRAM on the bit line is much smaller, so direct measurement is quite difficult. The proposed method will facilitate the measurement of the delay.
The measurement of the time required for the data stored in the capacitor (61) to be read at V.sub.0 is difficult due to the short delay time and small voltage variation. It is barely possible to observe the waveform directly on an oscilloscope. In addition, if the signal of the data is directly measured, the capacitance on the pad for measuring may be much larger than the total capacitance on the bit line. Therefore, a novel circuit and method are required to measure the short delay time of a DRAM.